1. Field of the Invention
The present invention relates to a semiconductor device including a thin film transistor (TFT) and a method for fabricating such a semiconductor device. More particularly, the present invention relates to a semiconductor device including a TFT, of which the channel forming region is a crystalline region obtained by crystallizing an amorphous semiconductor film, and a method for fabricating such a semiconductor device. The present invention is particularly effectively applicable for use in active-matrix-addressed liquid crystal displays (LCDs), organic EL displays, close-contact image sensors and three-dimensional ICs.
2. Description of the Related Art
To realize large-scale and high-resolution LCDs or organic EL displays and high-speed and high-resolution close-contact image sensors or three-dimensional ICs, research and development has been carried on extensively on the technique of forming a high-performance semiconductor device on an insulating substrate of glass, for example, or on an insulating film. Among other things, LCDs, including a pixel section and a driver circuit on the same substrate, have found applications in not just monitors for personal computers (PCs) but also various other types of household electronic appliances. For example, a cathode-ray tube (CRT), which used to be found as a TV monitor in almost every household, has been gradually replaced by a liquid crystal display. Also, a front projector for use to project a movie or a game video onto a screen or for any other amusement purpose has now become a household commodity which is not so hard to find. These are just samples representing a rapid growth of huge LCD markets. Meanwhile, so-called “systems-on-panel”, including a memory circuit and a logic circuit such as a clock generator on a glass substrate, is also being researched and developed intensively.
Generally speaking, to present a picture on a screen at a high resolution, the amount of information to be written onto each pixel should be increased significantly. Also, unless the enormous information is processible within a rather short time, pictures having such a huge amount of information as to achieve a high-definition display cannot be presented as moving pictures. Thus, to increase the processing rate sufficiently, a TFT for use in an LCD driver must operate at a tremendously increased speed. And to allow the TFT to operate at such a high speed, the TFT preferably includes a quality crystalline semiconductor film, of which the crystallinity is high enough to achieve sufficiently high field effect mobility.
The present inventors developed a technique of forming a quality semiconductor film with high crystallinity (i.e., of which the orientation directions of crystals are sufficiently aligned with each other) on a glass substrate by carrying out an annealing process at a lower temperature and in a shorter time than the conventional process. Specifically, the present inventors discovered that such a quality semiconductor film could be obtained by adding a metal element having the function of promoting the crystallization (which element will be referred to herein as a “catalytic element”) to an amorphous semiconductor film and then subjecting the amorphous semiconductor film to an annealing process.
However, it is known that if a TFT is made by using a crystalline silicon film, obtained by adding such a catalytic element, as its semiconductor layer as it is, then the TFT may experience an abrupt increase in OFF-state leakage current. The present inventors believe that this phenomenon should be caused by an irregular precipitation of the catalytic element in the semiconductor film (around the grain boundary, in particular). That is to say, the present inventors believe that those precipitates should form current leakage paths, thus increasing the OFF-state leakage current abruptly. To avoid such an unwanted sudden increase in OFF-state leakage current, after the crystalline silicon film has been formed, the concentration of the catalytic element in the crystalline silicon film needs to be decreased by removing the catalytic element from the silicon film. This process step of removing the catalytic element will be referred to herein as a “gettering process”.
Various gettering methods have been proposed. For example, Japanese Laid-Open Publication No. 10-270363 discloses a gettering technique of diffusing a catalytic element from its introduction site in a silicon film, which has been crystallized by the catalytic element added, to another site in the silicon film to which a Group Vb element such as phosphorus has been selectively introduced. This diffusion is achieved by annealing the silicon film. In this technique, an active region for a semiconductor device is defined in a portion of the silicon film to which the Group Vb element has not been introduced (i.e., the portion of which the concentration of the catalytic element has been decreased by the gettering process).
On the other hand, Japanese Laid-Open Publication No. 11-40499 discloses a technique of enhancing the catalytic element gettering effects by exposing the site, to which the Group Vb element has been selectively introduced, to an intense radiation such as a laser beam and then annealing the silicon film.
Furthermore, Japanese Laid-Open Publication No. 11-54760 discloses a technique of enhancing the catalytic element gettering effects by introducing not only the Group Vb element but also a Group IIIb element (e.g., born) into the same silicon film.
However, the conventional manufacturing process of semiconductor devices has the following drawbacks.
Firstly, the addition of the gettering process step increases the complexity and the cost of the manufacturing process. To overcome this problem, a method of selectively removing the catalytic element from the channel forming region only, not from the entire active region of the TFT, by diffusing the catalytic element to a portion of the active region to be the source or drain region was proposed.
In this method, the region to gather the catalytic element therein (which will be referred to herein as a “gettering region”) is a portion to be source or drain region (that portion will also be referred to herein as “source or drain region” for the sake of simplicity). For that purpose, the source or drain region is heavily doped with an element having the function of diffusing the catalytic element and belonging to Group Vb of the periodic table (such as phosphorus and arsenic, which will be referred to herein as a “gettering element” and which is also an n-type dopant element) and then subjected to an annealing process. As a result of this annealing process, the catalytic element is diffused toward the source or drain region, and the concentration of the catalytic element in the channel forming region decreases. In this case, if the source or drain region is also heavily doped with another dopant element belonging to Group IIIb of the periodic table (such as boron and aluminum, which is also a p-type dopant element), then the gettering effects can be enhanced as disclosed in Japanese Laid-Open Publication No. 11-54760 identified above.
In an n-channel TFT, if the source or drain region is used as a gettering region, the n-type dopant element belonging to Group Vb-(such as phosphorus) may function as the gettering element by itself. In a p-channel TFT, however, the p-type dopant element belonging to Group IIIb (such as boron) cannot function as the gettering element by itself. For that reason, the n-type dopant element belonging to Group Vb (such as phosphorus) also needs to be added as the gettering element to the source or drain region of the p-channel TFT. That is to say, in the p-channel TFT, the source or drain region that has been heavily doped with the n-type dopant element for the purpose of performing the gettering process on the catalytic element needs to have its conductivity type inverted into p-type (a process performed for that purpose is called a “counter-doping process”). To invert the conductivity type of the semiconductor layer of the p-channel TFT from n-type into p-type, the p-type dopant must be added about 1.5 to about 3.0 times as heavily as the n-type dopant by that counter-doping process. Accordingly, if the n-type dopant element belonging to Group Vb (such as phosphorus) is added at an increased level to enhance the gettering effects, then the p-type dopant element belonging to Group IIb (such as born) must be added at an abnormally high level. Such an outstandingly high doping level is above the processibility of a normal doping system. Consequently, the counter-doping process is far from being a mass-producible process.
Furthermore, the gettering effects can be enhanced by adding not only the n-type dopant element belonging to Group Vb (such as phosphorus) but also the p-type dopant element belonging to Group IIIb (such as boron) as described above. Accordingly, the gettering ability of an n-channel TFT may be different from that of a p-channel TFT. In that case, the rate at which the catalytic element is diffused from inside the semiconductor film into the gettering region in the n-channel TFT may be different from the diffusion rate of the catalytic element in the p-channel TFT, thus possibly creating a variation in device performance.
Also, the gettering process is carried out on the n-channel TFT with only the n-type dopant element belonging to Group Vb (such as phosphorus). Thus, sufficient gettering effects are not achievable (i.e., the concentration of the catalytic element remaining in the channel forming region of the TFT cannot be reduced sufficiently) for the n-channel TFT. The present inventors carried out experiments and actually modeled sample TFTs by the methods disclosed in Japanese Laid-Open Publications No. 10-270363 and No. 11-40499. As a result, several percent of the TFTs turned out to be defective, i.e., allowed a huge amount of leakage current to flow during the OFF state thereof, although the failure rate slightly varied with the specific method adopted. The present inventors analyzed the defective TFTs to find how the failure occurred. As a result, the present inventors discovered and confirmed via the experiments that a silicide was produced by the catalytic element around the junction between the channel forming region and the drain region. Thus, the gettering methods disclosed in the publications identified above cannot be regarded as highly productive or reliable techniques because the catalytic element cannot be removed sufficiently and because the failure rates are non-negligible although high-performance TFTs are obtained in fairly good numbers.
On the other hand, if the Group Vb dopant element and the Group IIIb dopant element are both added to the n-channel TFT as disclosed in Japanese Laid-Open Publication No. 11-54760, then the gettering effects can be enhanced to a certain degree. In that case, however, the n-type dopant element must be added more heavily than the p-type dopant element in the n-channel TFT. In the p-channel TFT on the other hand, the p-type dopant element must be added more heavily than the n-type dopant element. Thus, the manufacturing process is complicated significantly. In addition, dopants must be added at mutually different levels to the gettering region of the semiconductor layer that has one of two different conductivity types. Consequently, the gettering efficiency of the n-channel TFT is still different from that of the p-channel TFT.
Furthermore, it is already known that the increase in the OFF-state leakage current of the TFT is caused mainly due to the precipitation of the catalytic element around the junction between the channel forming region and the drain region. Accordingly, if the source and drain regions are used as the gettering regions, it is difficult to minimize the increase in the OFF-state leakage current of the TFT due to the catalytic element because the junction between the channel forming region and the source or drain region is also the boundary between the gettering region and the non-gettering region.